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CY29940-1
2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer
Features
* * * * * * * 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL-compatible inputs 18 clock outputs: drive up to 36 clock lines 150 ps max. output-to-output skew 23 output impedance Dual or single supply operation: -- 3.3V core and 3.3V outputs -- 3.3V core and 2.5V outputs -- 2.5V core and 2.5V outputs * Pin-compatible with MPC940L, MPC9109 * Available in commercial and industrial temperature ranges * 32-pin TQFP package
Description
The CY29940-1 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECLor a LVCMOS/LVTTL-compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL-compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS/LVTTL-compatible and can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output skews make the CY29940-1 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems.
Block Diagram
Pin Configuration
VDDC
VDD PECL_CLK PECL_CLK# TCLK TCLK_SEL 0 1
VDDC
VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 Q6 Q7 Q8 VDD Q9 Q10 Q11 VSS
18
VSS
Q0-Q17
TCLK TCLK_SEL PECL_CLK PECL_CLK# VDD VDDC
CY29940-1
VSS 21 20 19 18 17 VDDC
Q0
Q1
Q2
Q3
Q4 Q13
Q17
Q16
Q15
Q14
Cypress Semiconductor Corporation Document #: 38-07487 Rev. **
*
3901 North First Street
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San Jose, CA 95134 * 408-943-2600 Revised January 28, 2003
VSS
Q12
Q5
CY29940-1
Pin Description[1]
Pin 5 6 3 Name PECL_CLK PECL_CLK# TCLK VDDC PWR I/O I, PU PECL Input Clock I, PD PECL Input Clock I, PD External Reference/Test Clock Input O Clock Outputs Description
9, 10, 11, 13, Q(17:0) 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 4 8, 16, 29 7, 21 TCLK_SEL VDDC VDD
I, PD Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 3.3V or 2.5V Power Supply for Output Clock Buffers 3.3V or 2.5V Power Supply Common Ground
1, 2, 12, 17, 25 VSS
Note: 1. PD = Internal Pull-down; PU = Internal Pull-up.
Document #: 38-07487 Rev. **
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CY29940-1
Absolute Maximum Conditions
Maximum Input Voltage Relative to VSS: ............ VSS - 0.3V Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Storage Temperature: ................................-65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum ESD Protection............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
DC Electrical Specifications: VDD = 3.3V 5% or 2.5V 5%, VDDC = 3.3V 5% or 2.5V 5%
Parameter VIL VIH IIL IIH VPP VCMR VOL VOH IDDQ IDD Description Input Low Voltage Input High Voltage Input Low Current[2] 500 VDD = 3.3V VDD = 2.5V IOL = 20 mA, VDDC = 3.3V IOL = 16 mA, VDDC = 2.5V Output High Voltage[4,5,6] Quiescent Supply Current Dynamic Supply Current VDD = 3.3V, Outputs @ 150 MHz, CL=10 pF VDD = 3.3V, Outputs @ 200 MHz, CL=10 pF VDD = 2.5V, Outputs @ 150 MHz, CL=10 pF VDD = 2.5V, Outputs @ 200 MHz, CL=10 pF Zout Cin Output Impedance Input Capacitance 18 IOH = -20 mA, VDDC = 3.3V IOH = -16 mA, VDDC = 2.5V 2.4 1.8 5 285 335 200 240 23 4 28 pF 7 mA mA V VDD - 1.4 VDD - 1.0 Input High Current[2] Peak-to-Peak Input Voltage PECL_CLK Common Mode Range[3] PECL_CLK Output Low Voltage[4,5,6] Conditions Min. VSS 2.0 Typ. Max. 0.8 VDD -200 200 1000 VDD - 0.6 VDD - 0.6 0.5 V Unit V V A A mV V
Notes: 2. Inputs have pull-up/pull-down resistors that effect input current. 3. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the VCMR range and the input lies within the VPP specification. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. 4. Outputs driving 50 transmission lines. 5. See Figure 1 and Figure 2. 6. 50% input duty cycle.
Document #: 38-07487 Rev. **
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CY29940-1
AC Electrical Specifications (VDD = 3.3V 5% or 2.5V 5%, VDDC = 3.3V 5% or 2.5V 5%)[7]
Parameter Fmax TPD Description Input Frequency PECL_CLK to Q Delay[4,5,10] 134 MHz Output-to-Output Skew[4,5] Part-to-Part Skew[8] Part-to-Part Skew[8] Part to Part Skew[9] Output Clocks Rise/Fall Time[4,5] PECL, VDDC = 3.3V PECL, VDDC = 2.5V TCLK, VDDC = 3.3V TCLK, VDDC = 2.5V PECL_CLK TCLK 0.7V to 2.0V, VDDC = 3.3V 0.5V to 1.8V, VDDC = 2.5V 0.3 0.3 2.0 2.6 1.8 2.3 45 40 Min. Typ. Max. 200 180 4.0 5.2 3.4 4.0 55 60 150 1.4 2.2 1.2 1.7 850 750 1.1 1.3 ns ps ns ps ns % ns Unit MHz
CY29940-1 DUT
Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK CY29940-1 Test Reference for VCC = 3.3V and VCC = 2.5V
Zo = 50 ohm Differential Pulse Generator Z = 50 ohm
CY29940-1 DUT
Zo = 50 ohm
Zo = 50 ohm RT = 50 ohm RT = 50 ohm
VTT
VTT
Figure 2. PECL_CLK CY29940-1 Test Reference for VCC = 3.3V and VCC = 2.5V
Notes: 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 8. Across temperature and voltage ranges, includes output skew. 9. For a specific temperature and voltage, includes output skew. 10. Parameters tested @ 150 MHz.
Document #: 38-07487 Rev. **
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CY29940-1
VCC
VPP VCMR
PECL_CLK PECL_CLK
VCC /2
tP
VCC
GND
Q
T0 DC = tP / T0 x 100%
Figure 5. Output Duty Cycle (FoutDC)
VCC /2
tPD
GND
Figure 3. Propagation Delay (TPD) Test Reference
VCC VCC /2 GND VCC
VCC VCC /2 GND VCC VCC /2
LVCMOS_CLK
Q
VCC /2
tPD
GND
tSK(0)
Figure 6. Output-to-Output Skew tsk(0)
GND
Figure 4. LVCMOS Propagation Delay (TPD) Test Reference
Ordering Information
Part Number CY29940AC-1 CY29940AC-1T CY29940AI-1 CY29940AI-1T Package Type 32-pin TQFP 32-pin TQFP - Tape and Reel 32-pin TQFP 32-pin TQFP - Tape and Reel Production Flow Commercial, 0C to 70C Commercial, 0C to 70C Industrial, -40C to +85C Industrial, -40C to +85C
Document #: 38-07487 Rev. **
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CY29940-1
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.4 mm A32.14
51-85088-*B
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07487 Rev. **
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29940-1
Document History Page
Document Title: CY29940-1 2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer Document Number: 38-07487 REV. ** ECN NO. 119820 Issue Date 01/29/03 Orig. of Change BRK New Data Sheet Description of Change
Document #: 38-07487 Rev. **
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